The present invention concerns digital electronics and more particularly, to a method and a system to distribute clock signals in digital circuits.
A majority of digital circuits include pipelined systems, finite-state machines or a combination thereof. Storage elements incorporated in the pipelined systems and the finite-state machines are usually defined in terms of a set of clock waveforms used to control storage operations of each storage element.
For example, FIG. 1 shows an exemplary digital circuit, such as a Finite State Machine (FSM) 10. FSM 10 includes combinational logic 12 having one or more inputs 14 and one or more outputs 16. Some of the outputs, shown as 16a, are in electrical communication with some of the inputs, shown as 14a, through a storage element, shown as a register 18. Register 18 is clocked by one or more system clocks 20, which time the operation of FSM 10. FSM 10 operates by determining the xe2x80x9cnext statexe2x80x9d of register 18 as a function of the xe2x80x9ccurrent statexe2x80x9d of register 18 and the state at input 14. The state at outputs 16 are a function of the xe2x80x9ccurrent statexe2x80x9d of registers 18 and the state at inputs 14. Upon the sensing of a clock transition at CLK input, bits associated with the xe2x80x9cnext statexe2x80x9d propagate from output 16a to Dinput of register 18. Bits associated with the xe2x80x9ccurrent statexe2x80x9d propagate from Qoutput to input 14a. Next state bits replace current state bits, and the xe2x80x9ccurrent statexe2x80x9d bits are operated on by the combinational logic 12 to progress to outputs 16 and 16a. When the state of outputs 16 and 16a are stable, FSM 10 may be clocked again. The time required for state stabilization defines the maximum frequency that FSM 10 may operate.
FIG. 2 shows a pipelined system 22 that employs logic circuits 24a and 24b, as well as storage elements, e.g., registers 26a, 26b and 26c. Registers 26b and 26c receive the Qoutput of logic circuits 24a and 24b, respectively, during each clock cycle that is sensed by clock input CLK. Unlike FSM 10, shown above in FIG. 1, no feedback is incorporated in pipelined system 22, of FIG. 2.
Considering the dependence of digital circuits on a clock for proper operation, the importance of selecting a suitable clocking scheme becomes manifest. For example the clocking scheme, in part, dictates how many clock signals need to be routed throughout the digital circuit, as well as the configuration and design of the storage elements, e.g., how many transistors may be employed to fabricate the same. As a result, the clocking scheme impacts the size of, and the power dissipated by, the digital circuit.
Another consideration when selecting a suitable clocking scheme ensures that clock signals satisfy hold time and setup constraints. The hold time relates to a period of delay between a clock input to the register and the storage element in the registers. Data should be held during this period while the clock travels to the point of storage. The setup time is a period of delay between data input of the register and the storage element in the register. As the data takes a finite time to travel to the storage point, the clock should not change until the correct data value appears. Failure to satisfy the hold-time and setup constraints may result in erroneous data being stored in registers.
This can be problematic when synchronizing clock signals distributed to multiple storage elements, as in the case of a distributed-clock-tree scheme, shown in FIG. 3. The distributed-clock-tree scheme consists of a tree 30 of clock-buffers 32 with suitable geometry such that registers, shown as 34 and 36 receive well-regulated clock signals. However, RC delay in the clock path and/or delays in the clock-buffers, shown generally as delay1 and delay2, may cause clock signals to arrive at registers 34 and 36 asynchronously, referred to as clock skew.
Clock skew may cause both hold-time and setup violations. Assuming no delay is introduced by digital logic 38, the earliest that data appears at input Dinput of register 36 is at time Delay1+DelayQoutput, where DelayQoutput is the delay introduced by register 34. The clock is sensed by CLK input of register 36 at time Tc2. Assuming zero internal setup and hold times in the registers, were Tc2 greater than Tc1, where Tc1=Delay1+DelayQoutput, register 36 would store data from the current cycle rather than the previous cycle. This is a hold-time violation. Were Tc2 less than Tc1, data would arrive late at Dinput of register 36. This results in a setup-time violation.
A need exists, therefore, to provide a method and a system to distribute clock signals to a digital circuit that minimizes clock skew.
The present invention provides a method and a system to distribute clock signals in digital circuits to ensure that multiple clock signals reach multiple loads associated with the digital circuit, concurrently. To that end, an integrated digital circuit is provided having first and second sets of clock paths. The integrated digital circuit is mounted to a substrate that has a third set of clock paths. The multiple clock signals propagate through the first set of clock paths. One of the multiple clock signals is delayed with respect to the remaining clock signals, defining a propagational delay. The multiple clock signals are routed to the third set of clock paths contained on the substrate, defining routed clock signals. The third set of clock paths are configured to reduce, if not remove, the propagational delay in the routed signals that may result from the multiple clock signals propagating through the first or second sets of clock paths. To that end, the third set of clock paths are formed to have differing resistivities. This may be achieved by providing the clock paths of the third set with different lengths, different width or formed from differing materials, e.g., copper and aluminum. The routed clock signals propagating along the third set of clock paths are inputted to the second set of clock paths contained on the integrated digital circuit. The multiple loads of the integrated digital circuit are connected to receive the routed clock signals propagating along the second set of clock paths. In addition to minimizing delay between clock signals reaching the multiple loads, the advantages of coupling and decoupling the clock signals to clock paths on the substrate are manifold. Firstly, the number of clock paths, as well as clock buffers, required by the integrated digital circuit may be reduced. This reduces the number of elements that may introduce propagational delay and, therefore, clock skew. In addition, the dimensional tolerances for clock paths on the substrate are more relaxed than the dimensional tolerances for clock paths on the integrated digital circuit, while maintaining similarly, if not identical, operational characteristics. As a result, the cost associated with correcting propagational delays in clock signals is greatly reduced by reducing the same in the clock paths on the substrate.